SH7709S Datasheet, PDF (557/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Figures 16.2 to 16.4 show the SCIF I/O port pins.
SCIF pin I/O and data control is performed by bits 11 to 8 of SCPCR and bits 5 and 4 of SCPDR.
For details, see section 14.2.8, SC Port Control Register (SCPCR)/SC Port Data Register
(SCPDR).
SCPT[5]/SCK2
Reset
R
D
SCP5MD0
Q
C
PCRW
Reset
R
QD
SCP5MD1
C
PCRW
Reset
R
QD
SCP5DT1
C
PDRW
Internal data bus
SCIF
Clock input enable
Output enable
Serial clock output
PDRR*
Serial clock input
Legend
PDRW: SCPDR write
PDRR: SCPDR read
PCRW: SCPCR write
Note: * When reading the SCK2 pin, clear the CKE1 and CKE0
bits in SCSCR to 0, and set the SCP5MD1 bit in SCSPR to 1 (see section 14.2.8,
SC Port Control Register (SCPCR)/SC Port Data Register (SCPDR)).
Figure 16.2 SCPT[5]/SCK2 Pin
Rev. 5.00, 09/03, page 513 of 760