SH7709S Datasheet, PDF (236/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.6 Timing of STATUS Pin Changes
The timing of STATUS1 and STATUS0 pin changes is shown in figures 8.1 to 8.8.
8.6.1 Timing for Resets
Power-On Reset
CKIO, CKIO2*⁴
RESETP
PLL settling
time
STATUS
Normal*²
Reset*¹
Normal*²
RESETOUT
0 to 5 Bcyc*³
0 to 30 Bcyc*³
Notes: 1.
2.
3.
4.
Reset: HH (STATUS1 high, STATUS0 high)
Normal: LL (STATUS1 low, STATUS0 low)
Bcyc: Bus clock cycle
The CKIO2 output is available only in clock modes 0, 1, and 2.
Figure 8.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output
Rev. 5.00, 09/03, page 192 of 760