SH7709S Datasheet, PDF (298/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 5 to 3—Clock Select Bits (CKS2 to CKS0): Select the clock input to RTCNT. The source
clock is the external bus clock (CKIO). The RTCNT count clock is CKIO divided by the specified
ratio. RTCOR must be set before setting CKS2-CKS0.
Bit 5: CKS2
0
1
Bit 4: CKS1
0
1
0
1
Bit 3: CKS0
0
1
0
1
0
1
0
1
Description
Normal external bus clock
Clock input disabled
Bus clock (CKIO)/4
CKIO/16
CKIO/64
CKIO/256
CKIO/1024
CKIO/2048
CKIO/4096
Bit 2—Refresh Count Overflow Flag (OVF): Indicates when the number of refresh requests
indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS bit in RTCSR.
Bit 2: OVF
Description
0
RFCR has not exceeded the count limit value set in LMTS (Initial value)
Clearing condition: When 0 is written to OVF
1
RFCR has exceeded the count limit value set in LMTS
Setting condition: When the RFCR value has exceeded the count limit value
set in LMTS^*
Note: * Contents do not change when 1 is written to OVF.
Bit 1—Refresh Count Overflow Interrupt Enable (OVIE): Selects whether to suppress
generation of interrupt requests by the OVF bit in RTCSR when OVF is set to 1.
Bit 1: OVIE
0
1
Description
Interrupt request by OVF is disabled
Interrupt request by OVF is enabled
(Initial value)
Rev. 5.00, 09/03, page 254 of 760