SH7709S Datasheet, PDF (248/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

9.2 Overview of CPG
9.2.1 CPG Block Diagram
A block diagram of the on-chip clock pulse generator is shown in figure 9.1.
CAP1
CKIO
Cycle = Bcyc
CAP2
XTAL
EXTAL
Crystal
oscillator
Clock pulse generator
PLL circuit 1
(× 1, 2, 3, 4,
6)
PLL circuit 2
(× 1, 4)
Divider 1
×1
× 1/2
× 1/3
× 1/4
× 1/6
Internal
clock (Iφ)
Cycle = Icyc
Divider 2
×1
× 1/2
× 1/3
× 1/4
× 1/6
Peripheral
clock (Pφ)
Cycle = Pcyc
MD2
MD1
MD0
CPG control unit
Clock frequency
control circuit
Standby control
circuit
FRQCR
STBCR
Standby
control
Bus interface
Internal bus
Legend
FRQCR: Frequency control register STBCR: Standby control register
Figure 9.1 Block Diagram of Clock Pulse Generator
Rev. 5.00, 09/03, page 204 of 760