SH7709S Datasheet, PDF (318/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

When software wait insertion is specified by WCR2, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 10.11. A 2-cycle wait is specified as a software
wait. Sampling is performed at the transition from the Tw state to the T₂ state; therefore, if the
WAIT signal has no effect if asserted in the T₁ cycle or the first Tw cycle.
When the WAITSEL bit in the WCR1 register is set to 1, the WAIT signal is sampled at the
falling edge of the clock. If the setup time and hold times with respect to the falling edge of the
clock are not satisfied, the value sampled at the next falling edge is used.
However, the WAIT signal is ignored in the following three cases:
• A write to external address space in dual address mode with 16-byte DMA transfer
• Transfer from an external device with DACK to external address space in single address mode
with 16-byte DMA transfer
• Cache write-back access
Rev. 5.00, 09/03, page 274 of 760