SH7709S Datasheet, PDF (78/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Instruction Format
Source
Operand
Destination
Operand
nmd
format
15
0 mmmm: register
xxxx nnnn mmmm dddd ^direct
nnnndddd:
register
indirect with
displacement
mmmmdddd:
nnnn: register
register indirect direct
with displacement
d format
15
xxxx
xxxx
0 dddddddd: GBR
dddd dddd ^{indirect with}
displacement
R0 (register
direct)
R0 (register
direct)
dddddddd:
GBR indirect
with
displacement
dddddddd:
PC-relative with
displacement
R0 (register
direct)
dddddddd:
—
PC-relative
d12 format 15
0 dddddddddddd: —
xxxx dddd dddd dddd ^PC-relative
nd8 format 15
xxxx
i format 15
xxxx
nnnn
xxxx
dddd
iiii
0 dddddddd:
dddd ^{PC-relative with}
displacement
0 iiiiiiii: immediate
iiii
nnnn: register
direct
Indexed GBR
indirect
iiiiiiii: immediate
R0 (register
direct)
iiiiiiii: immediate —
ni format 15
0 iiiiiiii: immediate
xxxx nnnn i i i i i i i i
nnnn: register
direct
Note: * In a multiply-and-accumulate instruction, nnnn is the source register.
Instruction
Example
MOV.L
Rm,@(disp,Rn)
MOV.L
@(disp,Rm),Rn
MOV.L
@(disp,GBR),R
0
MOV.L
R0,@(disp,GBR
)
MOVA
@(disp,PC),R0
BF label
BRA label
(label = disp +
PC)
MOV.L
@(disp,PC),Rn
AND.B
#imm,
@(R0,GBR)
AND
#imm,R0
TRAPA #imm
ADD
#imm,Rn
Rev. 5.00, 09/03, page 34 of 760