SH7709S Datasheet, PDF (178/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 12—IRLS Enable (IRLSEN): Enables pins IRLS3–IRLS0. This bit is valid only when the
IRQLVL bit is 1.
Bit 12: IRLSEN Description
0
Pins IRLS3–IRLS0 disabled
1
Pins IRLS3–IRLS0 enabled
(Initial value)
Bits 11 and 10—IRQ5 Sense Select (IRQ51S, IRQ50S): Select whether the interrupt signal to
the IRQ5 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 11: IRQ51S Bit 10: IRQ50S Description
0
0
An interrupt request is detected at IRQ5 input falling edge
(Initial value)
1
An interrupt request is detected at IRQ5 input rising edge
1
0
An interrupt request is detected at IRQ5 input low level
1
Reserved
Bits 9 and 8—IRQ4 Sense Select (IRQ41S, IRQ40S): Select whether the interrupt signal to the
IRQ4 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 9: IRQ41S
0
1
Bit 8: IRQ40S
0
1
0
1
Description
An interrupt request is detected at IRQ4 input falling edge
(Initial value)
An interrupt request is detected at IRQ4 input rising edge
An interrupt request is detected at IRQ4 input low level
Reserved
Bits 7 and 6—IRQ3 Sense Select (IRQ31S, IRQ30S): Select whether the interrupt signal to the
IRQ3 pin is detected at the rising edge, at the falling edge, or at the low level.
Bit 7: IRQ31S
0
1
Bit 6: IRQ30S
0
1
0
1
Description
An interrupt request is detected at IRQ3 input falling edge
(Initial value)
An interrupt request is detected at IRQ3 input rising edge
An interrupt request is detected at IRQ3 input low level
Reserved
Rev. 5.00, 09/03, page 134 of 760