SH7709S Datasheet, PDF (126/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

(1) TLB Address Array Access
Read access
31
24 23
Address field
11110010 _*
31
Data field
VPN
17 16 12 11 10 9 8 7 6
0
* ^VPN * * ^{W 0} *
*
17 16 12 11 10 9 8 7
0
0
0 VPN 0 V
ASID
Write access
31
24 23
17 16 12 11 10 9 8 7 6
0
Address field
11110010 _*
* ^VPN * * ^{W 0} *
*
31
Data field
VPN
17 16 12 11 10 9 8 7
0
*
* ^VPN * ^V
ASID
VPN: Virtual page number
ASID: Address space identifier
V: Valid bit
* : Don't care bit
W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
(2) TLB Data Array Access
Read/write access
31
24 23
Address field
11110011 _*
31 29 28
Data field 000
PPN
17 16 12 11 10 9 8 7
0
* ^VPN * * ^W *
*
10 9 8 7 6 5 4 3 2 1 0
X V X PR SZ C D SH X
PPN:
PR:
C:
SH:
VPN:
X:
W:
Physical page number
V: Valid bit
Protection key field
SZ: Page-size bit
Cacheable bit
D: Dirty bit
Share status bit
* : Don't care bit
Virtual page number
0 for read, don’t care bit for write
Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
Figure 3.14 Specifying Address and Data for Memory-Mapped TLB Access
Rev. 5.00, 09/03, page 82 of 760