SH7709S Datasheet, PDF(244/807 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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SH7709S Datasheet, PDF (244/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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8.7.3 Hardware Standby Mode Timing

Figures 8.10 and 8.11 show examples of pin timing in hardware standby mode.

The CA pin is sampled using EXTAL2 (32.768 kHz), and a hardware standby request is only

recognized when the pin is low for two consecutive clock cycles.

The CA pin must be held low while the chip is in hardware standby mode.

Clock oscillation starts when the CA pin is driven high after the RESETP pin is driven low.

CKIO, CKIO2*6

Rcyc: EXTAL2 (32.768 kHz) cycle

CA

RESETP

STATUS

Normal*3

Standby*2

Undefined

Reset*1

2 Rcyc or more*5

0â10Bcyc*4

Notes: 1.

2.

3.

4.

5.

6.

Reset: HH (STATUS1 high, STATUS0 high)

Standby: LH (STATUS1 low, STATUS0 high)

Normal: LL (STATUS1 low, STATUS0 low)

Bcyc: Bus clock cycle

Rcyc: EXTAL2 (32.768 kHz) cycle

The CKIO2 output is available only in clock modes 0, 1, and 2.

Figure 8.10 Hardware Standby Mode

(When CA Goes Low in Normal Operation)

Rev. 5.00, 09/03, page 200 of 760

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