SH7709S Datasheet, PDF (160/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

In the following example, an address (32-bit) to be purged is specified in R0.
MOV.L #H'00000FF0, R1 ;
AND R0, R1
; The entry address is fetched.
MOV.L #H'F0000008, R2 ;
OR R1, R2
; The start is set to H'F0 and the A bit
to 1.
MOV.L #H'1FFFFC00, R3 ;
AND R0, R3
; The tag address is fetched. U = V = 0.
MOV.L R3, @R2
; Associative purge.
The above operation should be performed using a non-cacheable area.
(3) Reading Data from a Specific Entry
This example reads the data section of a specific entry. The longword in the data field of the data
array in figure 5.6 is read to the register.
; R0 = H'F100 004C; Data array access, Entry = H'04,
; Way = 0, Longword address = 3
;
MOV.L R0, @R1
; Longword 3 is read.
Rev. 5.00, 09/03, page 116 of 760