SH7709S Datasheet, PDF (286/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 15 to 13—Area 6 Wait Control (A6W2, A6W1, A6W0): Specify the number of wait states
inserted in physical space area 6. Also specify the number of states for burst transfer.
Bit 15:
A6W2
0
1
Bit 14:
A6W1
0
1
0
1
Bit 13:
A6W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Disabled
2
Enabled
1
Enabled
2
Enabled
2
Enabled
3
Enabled
3
Enabled
4
Enabled
4
Enabled
4
Enabled
6
Enabled
6
Enabled
8
Enabled
8
Enabled
10
Enabled
10
(Initial value)
Enabled
Bits 12 to 10—Area 5 Wait Control (A5W2, A5W1, A5W0): Specify the number of wait states
inserted in physical space area 5. Also specify the number of states for burst transfer.
Bit 12:
A5W2
0
1
Bit 11:
A5W1
0
1
0
1
Bit 10:
A5W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Disabled
2
Enabled
1
Enabled
2
Enabled
2
Enabled
3
Enabled
3
Enabled
4
Enabled
4
Enabled
4
Enabled
6
Enabled
6
Enabled
8
Enabled
8
Enabled
10
Enabled
10
(Initial value)
Enabled
Rev. 5.00, 09/03, page 242 of 760