SH7709S Datasheet, PDF (537/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 0—Smart Card Interface Mode Select (SMIF): Enables the smart card interface function.
Bit 0 : SMIF
0
1
Description
Smart card interface function disabled
Smart card interface function enabled
(Initial value)
15.2.2 Serial Status Register (SCSSR)
In smart card interface mode, the function of SCSSR bit 4 is changed. The setting conditions for
bit 2, the TEND bit, are also changed.
Bit: 7
6
5
4
3
TDRE RDRF ORER FER/ERS PER
Initial value: 1
0
0
0
0
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: Only 0 can be written, to clear the flag.
2
TEND
1
R
1
MPB
0
R
0
MPBT
0
R/W
Bit 7—Transmit Data Register Empty (TDRE)
Bit 6—Receive Data Register Full (RDRE)
Bit 5—Overrun Error (ORER)
These bits have the same function as in the ordinary SCI. See section 14, Serial Communication
Interface (SCI), for more information.
Bit 4—Error Signal Status (ERS): In the smart card interface mode, bit 4 indicates the state of
the error signal returned from the receiving side during transmission. The smart card interface
cannot detect framing errors.
Bit 4: ERS
Description
0
Receiving ended normally with no error signal
(Initial value)
[Clearing conditions]
(1) By a reset or in standby mode
(2) Cleared by reading ERS when ERS = 1, then writing 0 to ERS
1
An error signal indicating a parity error was transmitted from the receiving side
[Setting condition]
If the error signal sampled is low
Note: The ERS flag maintains its state even when the TE bit in SCSCR is cleared to 0.
Rev. 5.00, 09/03, page 493 of 760