SH7709S Datasheet, PDF (642/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

19.7.2 Port F Data Register (PFDR)
Bit: 7
PF7DT
Initial value: *
R/W: R
Note: * Undefined
6
PF6DT
*
R
5
PF5DT
*
R
4
PF4DT
*
R
3
PF3DT
*
R
2
PF2DT
*
R
1
PF1DT
*
R
0
PF0DT
*
R
The port F data register (PFDR) is an 8-bit read-only register that stores data for pins PTF7 to
PTF0. Bits PF7DT to PF0DT correspond to pins PTF7 to PTF0. When the function is general
input port, if the port is read the corresponding pin level is read. Table 19.12 shows the function of
PFDR.
PFDR is initialized by a power-on reset, after which the general input port function (pull-up MOS
on) is set as the initial pin function, and the corresponding pin levels are read.
Table 19.12 Port F Data Register (PFDR) Read/Write Operations
PFnMD1
0
1
PFnMD0
0
1
0
1
Pin State
Other function
(see table 18.1)
Reserved
Input (Pull-up
MOS on)
Input (Pull-up
MOS off)
Read
H'00
H'00
Pin state
Pin state
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
(n = 0 to 7)
Rev. 5.00, 09/03, page 598 of 760