SH7709S Datasheet, PDF (619/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

18.3.6 Port F Control Register (PFCR)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PF7 PF7 PF6 PF6 PF5 PF5 PF4 PF4 PF3 PF3 PF2 PF2 PF1 PF1 PF0 PF0
MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0 MD1 MD0
Initial value: 1/0 0 1/0 0 1/0 0 1/0 0 1 0 1 0 1 0 1 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
The port F control register (PFCR) is a 16-bit readable/writable register that selects the pin
functions. PFCR is initialized to H'AAAA (ASEMD0 = 1) or H'00AA (ASEMD0 = 0) by a power-
on reset, but is not initialized by a manual reset, in standby mode, or in sleep mode.
Bits 15 and 14—PF7 Mode 1 and 0 (PF7MD1, PF7MD0)
Bits 13 and 12—PF6 Mode 1 and 0 (PF6MD1, PF6MD0)
Bits 11 and 10—PF5 Mode 1 and 0 (PF5MD1, PF5MD0)
Bits 9 and 8—PF4 Mode 1 and 0 (PF4MD1, PF4MD0)
Bits 7 and 6—PF3 Mode 1 and 0 (PF3MD1, PF3MD0)
Bits 5 and 4—PF2 Mode 1 and 0 (PF2MD1, PF2MD0)
Bits 3 and 2—PF1 Mode 1 and 0 (PF1MD1, PF1MD0)
Bits 1 and 0—PF0 Mode 1 and 0 (PF0MD1, PF0MD0)
These bits select the pin functions and perform input pull-up MOS control.
Bit (2n + 1)
PFnMD1
0
0
1
1
Bit 2n
PFnMD0
0
1
0
1
Pin Function
Other function (see table 18.1)
Reserved
Port input (Pull-up MOS: on)
Port input (Pull-up MOS: off)
(Initial value) (ASEMD0 = 0)
(Initial value) (ASEMD0 = 1)
(n = 4 to 7)
Bit (2n + 1)
PFnMD1
0
0
1
1
Bit 2n
PFnMD0
0
1
0
1
Pin Function
Other function (see table 18.1)
Reserved
Port input (Pull-up MOS: on)
Port input (Pull-up MOS: off)
(Initial value)
(n = 0 to 3)
Rev. 5.00, 09/03, page 575 of 760