SH7709S Datasheet, PDF (385/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 6—DREQ Select Bit (DS): Selects low-level or falling-edge detection as the sampling method
for the DREQ pin used in external request mode.
This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and
CHCR3; 0 is read if this bit is read. The write value should always be 0.
In channels 0 and 1, if an on-chip peripheral module is specified as a transfer request source or an
auto-request is specified, the specification of this bit is ignored and falling-edge detection is fixed
except in an auto-request.
Bit 6: DS
0
1
Description
DREQ detected by low level
DREQ detected at falling edge
(Initial value)
Bit 5—Transmit Mode (TM): Specifies the bus mode when transferring data.
Bit 5: TM
0
1
Description
Cycle-steal mode
Burst mode
(Initial value)
Bits 4 and 3—Transmit Size Bits 1 and 0 (TS1, TS0): Specify the size of data to be transferred.
Bit 4: TS1
0
0
1
1
Bit 3: TS0
0
1
0
1
Description
Byte size (8 bits)
Word size (16 bits)
Longword size (32 bits)
16-byte unit (4 longword transfers)
(Initial value)
Bit 2—Interrupt Enable Bit (IE): If this bit is set to 1, an interrupt is requested on completion of
the number of data transfers specified in DMATCR (i.e. when TE = 1).
Bit 2: IE
0
1
Description
Interrupt request is not generated on completion of data transfers
specified in DMATCR
(Initial value)
Interrupt request is generated on completion of data transfers specified
in DMATCR
Rev. 5.00, 09/03, page 341 of 760