SH7709S Datasheet, PDF (381/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 31 to 21—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 20—Direct/Indirect Selection (DI): Selects direct address mode or indirect address mode in
channel 3.
This bit is only valid in CHCR3. Writing to this bit is invalid in CHCR0 to CHCR2; 0 is read if
this bit is read. The write value should always be 0. When using 16-byte transfer, direct address
mode must be specified. Operation is not guaranteed if indirect address mode is specified.
Bit 20: DI
0
1
Description
Direct address mode operation for channel 3
Indirect address mode operation for channel 3
(Initial value)
Bit 19—Source Address Reload Bit (RO): Selects whether the source address initial value is
reloaded in channel 2.
This bit is only valid in CHCR2. Writing to this bit is invalid in CHCR0, CHCR1, and CHCR3; 0
is read if this bit is read. The write value should always be 0. When using 16-byte transfer, this bit
must be cleared to 0, specifying non-reloading. Operation is not guaranteed if reloading is
specified.
Bit 19: RO
0
1
Description
Source address is not reloaded
Source address is reloaded
(Initial value)
Bit 18—Request Check Level Bit (RL): Specifies whether DRAK (DREQ acknowledge) signal
output is active-high or active-low.
This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and
CHCR3; 0 is read if this bit is read. The write value should always be 0.
Bit 18: RL
0
1
Description
Active-low DRAK output
Active-high DRAK output
(Initial value)
Rev. 5.00, 09/03, page 337 of 760