SH7709S Datasheet, PDF (472/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
• Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-
error interrupts are requested independently.
• When the SCI is not in use, it can be stopped by halting the clock supplied to it, saving power.
14.1.2 Block Diagram
Figure 14.1 shows a block diagram of the SCI.
Module data bus
Internal
data bus
RxD
TxD
SCK
SCRDR
SCRSR
SCTDR
SCPCR
SCBRR
SCPDR
SCSSR
SCTSR
SCSCR
SCSMR
Transmit/
receive
control
Baud rate
generator
Parity generation
Clock
Parity check
External clock
Legend
SCRSR: Receive shift register
SCRDR: Receive data register
SCTSR: Transmit shift register
SCTDR: Transmit data register
SCSMR: Serial mode register
SCI
SCSCR: Serial control register
SCSSR: Serial status register
SCBRR: Bit rate register
SCPDR: SC port data register
SCPCR: SC port control register
Figure 14.1 Block Diagram of SCI
Pφ
Pφ/4
Pφ/16
Pφ/64
TEI
TXI
RXI
ERI
Rev. 5.00, 09/03, page 428 of 760