SH7709S Datasheet, PDF (324/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Setting
External Address Pins
Bus Memory AMX AMX AMX AMX Output A1 to
Width Type 3 2 1 0 Timing A8 A9 A10 A11 A12 A13 A14 A15 A16
2M ×
0 1 0 1 Column A1 to A9 A10 L/H^*3 A12 A22^*4 A23^*4 A24
16bits ×
4banks^*2
address A8
Row
A10 to A18 A19 A20 A21 A22^*4 A23^*4 A24
address A17
1M ×
0 1 0 0 Column A1 to A9 A10 L/H^*3 A12 A21^*4 A22^*4 A15
16bits ×
address A8
4banks^*2
Row
A 9 to A17 A18 A19 A20 A21^*4 A22^*4 A23
address A16
2M ×
0 1 0 1 Column A1 to A9 A10 L/H^*3 A12 A22^*4 A23^*4 A24
8bits ×
address A8
4banks^*2
Row
A10 to A18 A19 A20 A21 A22^*4 A23^*4 A24
address A17
Notes: 1. Only RAL3L or CASL is output.
2. When addresses are upper 32 Mbytes, RAS3U or CASU is output.
When addresses are lower 32 Mbytes, RAS3L or CASL is output.
3. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
4. Bank address specification
Rev. 5.00, 09/03, page 280 of 760