SH7709S Datasheet, PDF (42/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 19.1 Port A Register ....................................................................................................... 587
Table 19.2 Port A Data Register (PADR) Read/Write Operations ........................................... 588
Table 19.3 Port B Register........................................................................................................ 589
Table 19.4 Port B Data Register (PBDR) Read/Write Operations ........................................... 590
Table 19.5 Port C Register........................................................................................................ 591
Table 19.6 Port C Data Register (PCDR) Read/Write Operations ........................................... 592
Table 19.7 Port D Register ....................................................................................................... 593
Table 19.8 Port D Data Register (PDDR) Read/Write Operations ........................................... 594
Table 19.9 Port E Register........................................................................................................ 595
Table 19.10 Port E Data Register (PEDR) Read/Write Operations ............................................ 596
Table 19.11 Port F Register ........................................................................................................ 597
Table 19.12 Port F Data Register (PFDR) Read/Write Operations ............................................ 598
Table 19.13 Port G Register ....................................................................................................... 599
Table 19.14 Port G Data Register (PGDR) Read/Write Operations ........................................... 600
Table 19.15 Port H Register ....................................................................................................... 601
Table 19.16 Port H Data Register (PHDR) Read/Write Operations ........................................... 602
Table 19.17 Port J Register......................................................................................................... 603
Table 19.18 Port J Data Register (PJDR) Read/Write Operations.............................................. 604
Table 19.19 Port K Register ....................................................................................................... 605
Table 19.20 Port K Data Register (PKDR) Read/Write Operations ........................................... 606
Table 19.21 Port L Register ........................................................................................................ 607
Table 19.22 Port L Data Register (PLDR) Read/Write Operation ............................................. 608
Table 19.23 SC Port Register ..................................................................................................... 609
Table 19.24 Read/Write Operation of the SC Port Data Register (SCPDR) .............................. 611
Table 20.1 A/D Converter Pins................................................................................................. 615
Table 20.2 A/D Converter Registers......................................................................................... 616
Table 20.3 Analog Input Channels and A/D Data Registers .................................................... 617
Table 20.4 A/D Conversion Time (Single Mode)..................................................................... 630
Table 20.5 Analog Input Pin Ratings........................................................................................ 634
Table 20.6 Relationship between Access Size and Read Data ................................................. 634
Table 21.1 D/A Converter Pins................................................................................................. 636
Table 21.2 D/A Converter Registers......................................................................................... 636
Table 22.1 UDI Registers ......................................................................................................... 643
Table 22.2 UDI Commands ...................................................................................................... 644
Table 22.3 Pins of this LSI and Boundary Scan Register Bits.................................................. 645
Table 22.4 Reset Configuration ................................................................................................ 652
Table 23.1 Absolute Maximum Ratings ................................................................................... 657
Table 23.2 DC Characteristics .................................................................................................. 659
Table 23.3 Permitted Output Current Values............................................................................ 662
Table 23.4 Operating Frequency Range ................................................................................... 663
Table 23.5 Clock Timing .......................................................................................................... 664
Table 23.6 Control Signal Timing ............................................................................................ 670
Table 23.7 Bus Timing ............................................................................................................. 673
Rev. 5.00, 09/03, page xlii of xliv