SH7709S Datasheet, PDF (287/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 9 to 7—Area 4 Wait Control (A4W2, A4W1, A4W0): Specify the number of wait states
inserted in physical space area 4.
Bit 9: A4W2
0
1
Bit 8: A4W1
0
1
0
1
Bit 7: A4W0
0
1
0
1
0
1
0
1
Description
Inserted Wait State WAIT Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
4
Enabled
6
Enabled
8
Enabled
10
Enabled (Initial value)
Bits 6 and 5—Area 3 Wait Control (A3W1, A3W0): Specify the number of wait states inserted
in physical space area 3.
• For Ordinary Memory
Bit 6: A3W1
0
1
Bit 5: A3W0
0
1
0
1
Description
Inserted Wait States WAIT Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled
(Initial value)
• For Synchronous DRAM
Bit 6: A3W1
0
1
Bit 5: A3W0
0
1
0
1
Description
Synchronous DRAM: CAS Latency
1
1
2
3
(Initial value)
Rev. 5.00, 09/03, page 243 of 760