SH7709S Datasheet, PDF (227/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

8.1.2 Pin Configuration
Table 8.2 lists the pins used for the power-down modes.
Table 8.2 Pin Configuration
Pin Name
Processing state 1
Processing state 0
Abbreviation I/O
STATUS1
O
STATUS0
Wakeup from
standby mode
WAKEUP
O
Note: H: high level; L: low level
Description
Operating state of the processor.
HH: Reset, HL: Sleep mode, LH: Standby mode,
LL: Normal operation
Active-low assertion after accepting wakeup
interrupt in standby mode until returning to normal
operation with WDT overflow
8.1.3 Register Configuration
Table 8.3 shows the control register configuration for the power-down modes.
Table 8.3 Register Configuration
Name
Abbreviation R/W Initial Value Access Size Address
Standby control register
STBCR
R/W H'00^*
H'FFFFFF82 8
Standby control register 2 STBCR2
R/W H'00^*
H'FFFFFF88 8
Note: * Initialized by a power-on reset. This value is not initialized by a manual reset; the current
value is retained.
8.2 Register Descriptions
8.2.1 Standby Control Register (STBCR)
The standby control register (STBCR) is an 8-bit readable/writable register that sets the power-
down mode. STBCR is initialized to H'00 by a power-on reset.
Bit: 7
6
STBY
—
Initial value: 0
0
R/W: R/W
R
5
4
3
— STBXTL —
0
0
0
R
R/W
R
2
1
0
MSTP2 MSTP1 MSTP0
0
0
0
R/W R/W R/W
Rev. 5.00, 09/03, page 183 of 760