SH7709S Datasheet, PDF (570/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 1—Receive FIFO Data Full (RDF): Indicates that receive data has been transferred to the
receive FIFO data register (SCFRDR), and the quantity of data in SCFRDR has become greater
than the receive trigger number specified by the RTRG1 and RTRG0 bits in the FIFO control
register (SCFCR).
Bit 1: RDF
Description
0
The quantity of transmit data written to SCFRDR is less than the specified
receive trigger number
(Initial value)
[Clearing conditions]
(1) By a power-on reset or in standby mode
(2) When the quantity of receive data in SCFRDR is less than the specified
receive trigger value and 1 is read from RDF, which is then cleared to 0
1
The quantity of receive data in SCFRDR is greater than the specified receive
trigger number
[Setting condition]
When a quantity of receive data greater than the specified receive trigger number
is stored in SCFRDR^*
Note: * Since SCFTDR is a 16-byte FIFO register, the maximum quantity of data that can be read
when RDF is 1 is the specified receive trigger number. If an attempt is made to read after
all the data in SCFRDR has been read, the data is undefined. The quantity of receive data
in SCFRDR is indicated by the lower 8 bits of SCFTDR.
Bit 0—Receive Data Ready (DR): Indicates that the quantity of data in the receive FIFO data
register (SCFRDR) is less than the specified receive trigger number, and that the next data has not
yet been received after the elapse of 15 etu from the last stop bit.
Bit 0: DR
Description
0
Receiving is in progress, or no receive data remains in SCFRDR after receiving
ended normally
(Initial value)
[Clearing conditions]
(1) When the chip undergoes a power-on reset or enters standby mode
(2) When software reads DR after it has been set to 1, then writes 0 to DR
1
Next receive data has not been received
[Setting condition]
When SCFRDR contains less data than the specified receive trigger number,
and the next data has not yet been received after the elapse of 15 etu from the
last stop bit^*
Note: * This is equivalent to 1.5 frames with the 8-bit, 1-stop-bit format. (etu: elementary time unit)
Rev. 5.00, 09/03, page 526 of 760