SH7709S Datasheet, PDF (326/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

independently for areas 2 and 3 by means of bits A2W1 and A2W0 or A3W1 and A3W0 in
WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency
cycles.
Tr
CKIO
A25 to A16,
A13
A12
A15, A14,
A11 to A0
CS2 or CS3
RAS3x
CASx
RD/WR
DQMxx
D31 to D0
BS
Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4
Tpc
Figure 10.14 Basic Timing for Synchronous DRAM Burst Read
Rev. 5.00, 09/03, page 282 of 760