SH7709S Datasheet, PDF (556/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

16.1.2 Block Diagram
Figure 16.1 shows a block diagram of the SCIF.
Module data bus
Internal
data bus
RxD
TxD
SCK
SCFRDR2
(16
stages)
Receive
buffer
SCRSR
SCFTDR2
(16
stages)
SCPCR
SCFDR
SCFDR2
SCFCR2
SCBRR
Transmit
buffer
SCSSR2
SCSCR2
SCSMR2
Baud rate
generator
SCTSR
Transmit/
receive
control
Parity generation
Clock
Parity check
External clock
SCIF
Pφ
Pφ/4
Pφ/16
Pφ/64
TEI
TXI
RXI
BRI
Legend
SCRSR: Receive shift register
SCFRDR2: Receive FIFO data register 2
SCTSR: Transmit shift register
SCFTDR2: Transmit FIFO data register 2
SCSMR2: Serial mode register 2
SCSCR2: Serial control register 2
SCSSR2: Serial status register 2
SCBRR2: Bit rate register 2
SCFCR2: FIFO control register 2
SCFDR2: FIFO data count register 2
SCPDR: Port SC data register
SCPCR: Port SC control register
Figure 16.1 Block Diagram of SCIF
Rev. 5.00, 09/03, page 512 of 760