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| SH7709S Datasheet, PDF (722/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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23.3.5 Burst ROM Timing
T1
TB2
TB1
TB2
TB1
TB2
TB1
T2
CKIO
tAD
A25 to A4
tAD
tAD
A3 to A0
tCSD1
CSn
tRWD
RD/WR
tRSD tRSD tAH
RD
tRDH1
tRDS
D31 to D0
tBSD
tBSD
tBSD
tBSD
BS
DACKn
tDAKD1
WAIT
tWTS tWTH
tWTS tWTH
tAD
tAH
tCSD2 tRWH
tRDH1
tRWD
tRSD
tAH
tRSD tRWH
tRDS1
tRDH1
tDAKD2
tWTS tWTH
Note: In the write cycle, the basic bus cycle, the basic bus cycle is performed.
Figure 23.19 Burst ROM Bus Cycle (No Wait)
Rev. 5.00, 09/03, page 678 of 760
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