SH7709S Datasheet, PDF (212/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 30 to 28—Instruction Decode Pointer (PID2 to PID0): PID is a 3-bit binary pointer (0–7).
These bits indicate the instruction buffer number which stores the last executed instruction before
branch.
Bits 30 to 28:
PID
Even
Odd
Description
PID indicates the instruction buffer number.
PiD+2 indicates the instruction buffer number
Bits 27 to 0—Branch Source Address (BSA27 to BSA0): These bits store the last fetched
address before branch.
7.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the
flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and
also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight
BRDR registers have queue structure and a stored register is shifted every branch.
Bit: 31
30
29
28
27
26
25
24
DVF
—
—
— BDA27 BDA26 BDA25 BDA24
Initial value: 0
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
23
BDA23
*
R
22
BDA22
*
R
21
BDA21
*
R
20
BDA20
*
R
19
BDA19
*
R
18
BDA18
*
R
17
BDA17
*
R
16
BDA16
*
R
Bit:
Initial value:
R/W:
15
BDA15
*
R
14
BDA14
*
R
13
BDA13
*
R
12
BDA12
*
R
11
BDA11
*
R
10
BDA10
*
R
9
BDA9
*
R
8
BDA8
*
R
Bit: 7
BDA7
Initial value: *
R/W: R
Note: * Undefined value
6
BDA6
*
R
5
BDA5
*
R
4
BDA4
*
R
3
BDA3
*
R
2
BDA2
*
R
1
BDA1
*
R
0
BDA0
*
R
Rev. 5.00, 09/03, page 168 of 760