SH7709S Datasheet, PDF (18/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

3.4 MMU Functions ................................................................................................................ 69
3.4.1 MMU Hardware Management ............................................................................. 69
3.4.2 MMU Software Management............................................................................... 69
3.4.3 MMU Instruction (LDTLB) ................................................................................. 70
3.4.4 Avoiding Synonym Problems............................................................................... 72
3.5 MMU Exceptions .............................................................................................................. 74
3.5.1 TLB Miss Exception ............................................................................................ 74
3.5.2 TLB Protection Violation Exception.................................................................... 75
3.5.3 TLB Invalid Exception......................................................................................... 76
3.5.4 Initial Page Write Exception ................................................................................ 77
3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow
for Address Error) ................................................................................................ 79
3.6 Configuration of Memory-Mapped TLB........................................................................... 80
3.6.1 Address Array ...................................................................................................... 80
3.6.2 Data Array ............................................................................................................ 81
3.6.3 Usage Examples ................................................................................................... 83
3.7 Usage Note ........................................................................................................................ 83
Section 4 Exception Handling.......................................................................................... 85
4.1 Overview ........................................................................................................................... 85
4.1.1 Features ................................................................................................................ 85
4.1.2 Register Configuration ......................................................................................... 85
4.2 Exception Handling Function............................................................................................ 85
4.2.1 Exception Handling Flow..................................................................................... 85
4.2.2 Exception Vector Addresses................................................................................. 86
4.2.3 Acceptance of Exceptions .................................................................................... 88
4.2.4 Exception Codes................................................................................................... 90
4.2.5 Exception Request Masks .................................................................................... 91
4.2.6 Returning from Exception Handling .................................................................... 91
4.3 Register Descriptions......................................................................................................... 92
4.4 Exception Handling Operation .......................................................................................... 93
4.4.1 Reset..................................................................................................................... 93
4.4.2 Interrupts .............................................................................................................. 93
4.4.3 General Exceptions............................................................................................... 94
4.5 Individual Exception Operations ....................................................................................... 94
4.5.1 Resets ................................................................................................................... 94
4.5.2 General Exceptions............................................................................................... 95
4.5.3 Interrupts .............................................................................................................. 99
4.6 Cautions............................................................................................................................. 100
Section 5 Cache .................................................................................................................... 103
5.1 Overview ........................................................................................................................... 103
5.1.1 Features ................................................................................................................ 103
Rev. 5.00, 09/03, page xviii of xliv