SH7709S Datasheet, PDF (317/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 10.2.4, Wait
State Control Register 2 (WCR2).
The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing
shown in figure 10.10.
CKIO
T₁
Tw
T₂
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn
D31 to D0
BS
Figure 10.10 Basic Interface Wait Timing (Software Wait Only)
Rev. 5.00, 09/03, page 273 of 760