SH7709S Datasheet, PDF (158/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

The following two operations on the data array are possible. Note that these operations will not
change the information in the address array.
(1) Data Array Read
Reads the data at the position selected by the L bits (3-2) of the address field from the entry that
corresponds to the entry address and way that were specified in the address field.
(2) Data Array Write
Writes the longword data set in the data field into the entry that corresponds to the entry address
and way that were specified in the address field. The longword data will be written to the entry at
the position selected by the L bits (3-2) of the address field.
1. Address array access
Address specification
Read access
31
24
1111 0000
23
14
*^{…………}*
13 12
W
11
4
Entry address
Write access
31
24
1111 0000
23
14
*^{…………}*
13 12
W
11
4
Entry address
3
2
0
0* * *
3
2
0
A_{* * *}
Data specification (both read and write accesses)
31 30 29
10 9
4
0 0 0 Address tag (28−10)
LRU
3
2
XX
1
0
UV
2. Data array access (both read and write accesses)
Address specification
31
24
1111 0001
23
14
*^{…………}*
13 12
W
11
4
Entry address
3
21
0
L
00
Data specification
31
0
Longword
X: 0 for read, don't care for write
*: Don't care bit
Figure 5.6 Specifying Address and Data for Memory-Mapped Cache Access
Rev. 5.00, 09/03, page 114 of 760