SH7709S Datasheet, PDF (696/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

22.4.2 Reset Configuration
Table 22.4 Reset Configuration
ASEMD0^*1
RESETP
TRST
Chip State
High-level
Low-level
Low-level
Normal reset and UDI reset
High-level
Normal reset
High-level
Low-level
UDI reset only
Low-level
Low-level
High-level
Low-level
High-level
Normal operation
Reset hold^*2
ASE user mode^*3: Normal reset
ASE break mode^*3: RESETP assertion
masked
High-level
Low-level
UDI reset only
High-level
Normal operation
Notes: 1. Selects main chip mode or ASE mode
ASEMD0 = H, normal mode
ASEMD0 = L, ASE mode
Set ASEMD0 = H when using on the user system alone, without an emulator and the
UDI.
2. In ASE mode, reset hold is enabled by driving the RESETP and TRST pins low for a
constant cycle. In this state, the CPU does not start up, even if RESETP is driven high.
When TRST is driven high, UDI operation is enabled, but the CPU does not start up.
The reset hold state is cancelled by the following:
• Boot request from UDI
• Another RESETP assert (power-on reset)
3. There are two ASE modes, one for executing software in the emulator’s firmware (ASE
break mode) and one for executing user software (ASE user mode).
Rev. 5.00, 09/03, page 652 of 760