SH7709S Datasheet, PDF (28/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

19.11.1 Register Description ............................................................................................. 605
19.11.2 Port K Data Register (PKDR) .............................................................................. 606
19.12 Port L................................................................................................................................. 607
19.12.1 Register Description ............................................................................................. 607
19.12.2 Port L Data Register (PLDR) ............................................................................... 608
19.13 SC Port .............................................................................................................................. 609
19.13.1 Register Description ............................................................................................. 609
19.13.2 SC Port Data Register (SCPDR) .......................................................................... 610
Section 20 A/D Converter ................................................................................................. 613
20.1 Overview ........................................................................................................................... 613
20.1.1 Features ................................................................................................................ 613
20.1.2 Block Diagram ..................................................................................................... 614
20.1.3 Input Pins.............................................................................................................. 615
20.1.4 Register Configuration ......................................................................................... 616
20.2 Register Descriptions......................................................................................................... 617
20.2.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 617
20.2.2 A/D Control/Status Register (ADCSR) ................................................................ 618
20.2.3 A/D Control Register (ADCR)............................................................................. 621
20.3 Bus Master Interface.......................................................................................................... 622
20.4 Operation........................................................................................................................... 623
20.4.1 Single Mode (MULTI = 0)................................................................................... 623
20.4.2 Multi Mode (MULTI = 1, SCN = 0) .................................................................... 625
20.4.3 Scan Mode (MULTI = 1, SCN = 1) ..................................................................... 627
20.4.4 Input Sampling and A/D Conversion Time .......................................................... 629
20.4.5 External Trigger Input Timing ............................................................................. 630
20.5 Interrupts ........................................................................................................................... 631
20.6 Definitions of A/D Conversion Accuracy ......................................................................... 631
20.7 Usage Notes....................................................................................................................... 632
20.7.1 Setting Analog Input Voltage ............................................................................... 632
20.7.2 Processing of Analog Input Pins .......................................................................... 632
20.7.3 Access Size and Read Data .................................................................................. 633
Section 21 D/A Converter ................................................................................................. 635
21.1 Overview ........................................................................................................................... 635
21.1.1 Features ................................................................................................................ 635
21.1.2 Block Diagram ..................................................................................................... 635
21.1.3 I/O Pins................................................................................................................. 636
21.1.4 Register Configuration ......................................................................................... 636
21.2 Register Descriptions......................................................................................................... 637
21.2.1 D/A Data Registers 0 and 1 (DADR0/1) .............................................................. 637
21.2.2 D/A Control Register (DACR)............................................................................. 637
21.3 Operation........................................................................................................................... 639
Rev. 5.00, 09/03, page xxviii of xliv