SH7709S Datasheet, PDF (736/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Tp
Tpw
Tr
Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4
CKIO
A25 to A16
A12 or A10
A15 to A0
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
t_AD
t_AD
t_AD
t_AD
t_CSD3
Row address
t_AD
Row
address
t_AD
Row
address
Read command
Column address
t_RWD
t_RWD
t_RASD2
t_RASD2
t_RASD2
t_RASD2
t_CASD2
t_DQMD
t_DQMD
t_RDS2 t_RDH2
t_BSD
t_AD
t_AD
t_AD
t_CSD3
t_RWD
t_CASD2
t_DQMD
t_RDS2 t_RDH2
t_BSD
CKE
DACKn
(High)
tDAKD1
tDAKD1
Figure 23.33 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1)
Rev. 5.00, 09/03, page 692 of 760