SH7709S Datasheet, PDF (81/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Operation
Classification Types Code
Function
Branch
9
BF
Conditional branch, delayed conditional
branch (T = 0)
BT
Conditional branch, delayed conditional
branch (T = 1)
BRA
Unconditional branch
BRAF
Unconditional branch
BSR
Branch to subroutine procedure
BSRF
Branch to subroutine procedure
JMP
Unconditional branch
JSR
Branch to subroutine procedure
RTS
Return from subroutine procedure
System
control
15
CLRMAC MAC register clear
CLRT
Clear T bit
CLRS
Clear S bit
LDC
Load to control register
LDS
Load to system register
LDTLB
Load PTE to TLB
NOP
No operation
PREF
Prefetch data to cache
RTE
Return from exception handling
SETS
Set S bit
SETT
Set T bit
SLEEP Shift to power-down mode
STC
Store from control register
STS
Store from system register
TRAPA Trap exception handling
Total: 68
No. of
Instructions
11
75
188
Rev. 5.00, 09/03, page 37 of 760