SH7709S Datasheet, PDF (86/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Instruction
DMULS.L Rm,Rn
DMULU.L Rm,Rn
DT
Rn
EXTS.B Rm,Rn
EXTS.W Rm,Rn
EXTU.B Rm,Rn
EXTU.W Rm,Rn
MAC.L @Rm+,@Rn+
MAC.W @Rm+,@Rn+
MUL.L Rm,Rn
MULS.W Rm,Rn
MULU.W Rm,Rn
Operation
Code
Signed operation of
0011nnnnmmmm1101
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
Unsigned operation of 0011nnnnmmmm0101
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
Rn – 1 → Rn, if Rn =
0, 1 → T, else 0 → T
0100nnnn00010000
A byte in Rm is sign-
extended → Rn
0110nnnnmmmm1110
A word in Rm is sign-
extended → Rn
0110nnnnmmmm1111
A byte in Rm is zero-
extended → Rn
0110nnnnmmmm1100
A word in Rm is zero-
extended → Rn
0110nnnnmmmm1101
Signed operation of (Rn)
× (Rm) + MAC → MAC,
Rn + 4 → Rn,
Rm + 4 → Rm,
32 × 32 + 64 → 64 bits
0000nnnnmmmm1111
Signed operation of (Rn)
× (Rm) + MAC → MAC,
Rn + 2 → Rn,
Rm + 2 → Rm,
16 × 16 + 64 → 64 bits
0100nnnnmmmm1111
Rn × Rm → MACL,
32 × 32 → 32 bits
0000nnnnmmmm0111
Signed operation of Rn
× Rm → MACL,
16 × 16 → 32 bits
0010nnnnmmmm1111
Unsigned operation of
Rn × Rm → MACL,
16 × 16 → 32 bits
0010nnnnmmmm1110
Privileged
Mode
Cycles T Bit
—
2(to 5)^* —
—
2(to 5)^* —
—
1
Comparison
result
—
1
—
—
1
—
—
1
—
—
1
—
—
2(to 5)^* —
—
2(to 5)^* —
—
2(to 5)^* —
—
1(to 3)^* —
—
1(to 3)^* —
Rev. 5.00, 09/03, page 42 of 760