SH7709S Datasheet, PDF (288/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bits 4 and 3—Area 2 Wait Control (A2W1, A2W0): Specify the number of wait states inserted
in physical space area 2.
• For Ordinary Memory
Bit 4: A2W0
0
1
Bit 3: A2W0
0
1
0
1
Description
Inserted Wait States
WAIT Pin
0
Ignored
1
Enabled
2
Enabled
3
Enabled (Initial value)
• For Synchronous DRAM
Bit 4: A2W1
0
1
Bit 3: A2W0
0
1
0
1
Description
Synchronous DRAM: CAS Latency
1
1
2
3
(Initial value)
Bits 2 to 0—Area 0 Wait Control (A0W2, A0W1, A0W0): Specify the number of wait states
inserted in physical space area 0. Also specify the burst pitch for burst transfer.
Bit 2:
A0W2
0
1
Bit 1:
A0W1
0
1
0
1
Bit 0:
A0W0
0
1
0
1
0
1
0
1
Description
First Cycle
Burst Cycle
(Excluding First Cycle)
Inserted
Wait States
WAIT Pin
Number of States
Per Data Transfer WAIT Pin
0
Ignored
2
Enabled
1
Enabled
2
Enabled
2
Enabled
3
Enabled
3
Enabled
4
Enabled
4
Enabled
4
Enabled
6
Enabled
6
Enabled
8
Enabled
8
Enabled
10
Enabled
10
(Initial value)
Enabled
Rev. 5.00, 09/03, page 244 of 760