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| SH7709S Datasheet, PDF (724/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series | |||
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T1
Tw
Tw
TB2
TB1
TBw
T2
CKIO
tAD
A25 to A4
tAD
tAD
A3 to A0
CSn
tCSD1
RD/WR
RD
tRWD
tRSD
D31 to D0
tBSD
tBSD
tAH
tCSD2 tRWH
tRSD1 tAH tRSD1
tRDH1
tRWD
tAH
tRSD tRWH
tRDS1
tRDH1
tRDS
tRDH1
tBSD tBSD
BS
DACKn
WAIT
tDAKD1
tWTS tWTH
tWTS tWTH
tDAKD2
tWTS tWTH
tWTS tWTH
Note: In the write cycle, the basic bus cycle is performed.
Figure 23.21 Burst ROM Bus Cycle (External Wait, WAITSEL = 1)
Rev. 5.00, 09/03, page 680 of 760
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