SH7709S Datasheet, PDF (136/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

4.3 Register Descriptions
There are four registers related to exception handling. These are peripheral module registers, and
therefore reside in area P4. They can be accessed by specifying the address in privileged mode
only.
1. The exception event register (EXPEVT) resides at address H'FFFFFFD4, and contains a 12-bit
exception code. The exception code set in EXPEVT is that for a reset or general exception
event. The exception code is set automatically by hardware when an exception occurs.
EXPEVT can also be modified by software.
2. The interrupt event register (INTEVT) resides at address H'FFFFFFD8, and contains a 12-bit
interrupt exception code or a code indicating the interrupt priority. Which is set when an
interrupt occurs depends on the interrupt source (see tables 6.4 and 6.5). The exception code or
interrupt priority code is set automatically by hardware when an exception occurs. INTEVT
can also be modified by software.
3. Interrupt event register 2 (INTEVT2) resides at address H'04000000, and contains a 12-bit
exception code. The exception code set in INTEVT2 is that for an interrupt request. The
exception code is set automatically by hardware when an exception occurs.
4. The TRAPA exception register (TRA) resides at address H'FFFFFFD0, and contains 8-bit
immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when
a TRAPA instruction is executed. TRA can also be modified by software.
The bit configurations of the EXPEVT, INTEVT, INTEVT2, and TRA registers are shown in
figure 4.3.
EXPEVT, INTEVT, and INTEVT2 registers
31
11
0
0
0 Exception code
TRA register
31
0
9
20
0 imm 00
0: Reserved bits, always read as 0
imm: 8-bit immediate data in TRAPA instruction
Figure 4.3 Bit Configurations of EXPEVT, INTEVT, INTEVT2, and TRA Registers
Rev. 5.00, 09/03, page 92 of 760