SH7709S Datasheet, PDF (139/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

• UDI Reset
 Conditions: UDI reset command input (see section 22.4.3, UDI Reset)
 Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000.
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip peripheral
modules are initialized. See the register descriptions in the relevant sections for details.
Table 4.4 Types of Reset
Type
Power-on
reset
Manual
reset
UDI
reset
Conditions for Transition
to Reset State
RESETP = Low
RESETM = Low
UDI reset command input
CPU
Initialized
Initialized
Initialized
Internal State
On-Chip Peripheral Modules
(See register configuration in
relevant sections)
4.5.2 General Exceptions
• TLB miss exception
 Conditions: Comparison of TLB addresses shows no address match.
 Operations: The virtual address (32 bits) that caused the exception is set in TEA and the
corresponding virtual page number (22 bits) is set in PTEH (31–10). The ASID of PTEH
indicates the ASID at the time the exception occurred. If all ways are valid, 1 is added to
the RC bit in MMUCR. If there is one or more invalid way, they are set by priority starting
with way 0.
PC and SR of the instruction that generated the exception are saved to SPC and SSR,
respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception
occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1
and a branch occurs to PC = VBR + H'0400.
To speed up TLB miss processing, the offset differs from other exceptions.
Rev. 5.00, 09/03, page 95 of 760