SH7709S Datasheet, PDF (33/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

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Synchronous DRAM Mode Write Timing ........................................................... 303
Burst ROM Wait Access Timing ......................................................................... 305
Burst ROM Basic Access Timing ........................................................................ 306
Example of PCMCIA Interface ............................................................................ 308
Basic Timing for PCMCIA Memory Card Interface ............................................ 310
Wait Timing for PCMCIA Memory Card Interface ............................................. 311
Basic Timing for PCMCIA Memory Card Interface Burst Access ...................... 312
Wait Timing for PCMCIA Memory Card Interface Burst Access ....................... 313
PCMCIA Space Allocation .................................................................................. 314
Basic Timing for PCMCIA I/O Card Interface .................................................... 316
Wait Timing for PCMCIA I/O Card Interface ..................................................... 317
Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................ 318
Waits between Access Cycles .............................................................................. 320
Pull-Up Timing for Pins A25 to A0 ..................................................................... 321
Pull-Up Timing for Pins D31 to D0 (Read Cycle) ............................................... 322
Pull-Up Timing for Pins D31 to D0 (Write Cycle) .............................................. 322
Block Diagram of DMAC .................................................................................... 329
DMAC Transfer Flowchart .................................................................................. 346
Round-Robin Mode.............................................................................................. 350
Changes in Channel Priority in Round-Robin Mode............................................ 351
Operation of Direct Address Mode in Dual Address Mode ................................. 353
Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
(Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory). 354
Indirect Address Operation in Dual Address Mode (When External Memory
Space has a 16-Bit Width).................................................................................... 355
Example of Transfer Timing in the Indirect Address Mode in Dual Address
Mode .................................................................................................................... 356
Data Flow in Single Address Mode...................................................................... 357
Example of DMA Transfer Timing in Single Address Mode .............................. 358
Example of DMA Transfer Timing in Single Address Mode (16-byte Transfer,
External Memory Space (Ordinary Memory) → External Device with DACK) . 359
Example of DMA Transfer in Cycle-Steal Mode................................................. 360
Example of Transfer in Burst Mode ..................................................................... 360
Bus State when Multiple Channels Are Operating............................................... 362
Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) ..................................... 365
Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) ..................................... 366
Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access:
4 Cycles)............................................................................................................... 367
Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) . 368
Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) ...................................... 369
Burst Mode, Level Input ...................................................................................... 370
Burst Mode, Edge Input ....................................................................................... 371
Source Address Reload Function Diagram........................................................... 372
Rev. 5.00, 09/03, page xxxiii of xliv