SH7709S Datasheet, PDF (196/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

7.2 Register Descriptions
7.2.1 Break Address Register A (BARA)
BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in
channel A. A power-on reset initializes BARA to H'00000000.
Bit:
Initial value:
R/W:
31
BAA31
0
R/W
30
BAA30
0
R/W
29
BAA29
0
R/W
28
BAA28
0
R/W
27
BAA27
0
R/W
26
BAA26
0
R/W
25
BAA25
0
R/W
24
BAA24
0
R/W
Bit:
Initial value:
R/W:
23
BAA23
0
R/W
22
BAA22
0
R/W
21
BAA21
0
R/W
20
BAA20
0
R/W
19
BAA19
0
R/W
18
BAA18
0
R/W
17
BAA17
0
R/W
16
BAA16
0
R/W
Bit:
Initial value:
R/W:
15
BAA15
0
R/W
14
BAA14
0
R/W
13
BAA13
0
R/W
12
BAA12
0
R/W
11
BAA11
0
R/W
10
BAA10
0
R/W
9
BAA9
0
R/W
8
BAA8
0
R/W
Bit:
Initial value:
R/W:
7
BAA7
0
R/W
6
BAA6
0
R/W
5
BAA5
0
R/W
4
BAA4
0
R/W
3
BAA3
0
R/W
2
BAA2
0
R/W
1
BAA1
0
R/W
0
BAA0
0
R/W
Bits 31 to 0—Break Address A31 to A0 (BAA31 to BAA0): Stores the address on the LAB or
IAB specifying break conditions of channel A.
Rev. 5.00, 09/03, page 152 of 760