SH7709S Datasheet, PDF (479/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in asynchronous mode. In the
synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 6: CHR
Description
0
8-bit data
1
7-bit data^*
(Initial value)
Note: * When 7-bit data is selected, the MSB (bit 7) of the transmit data register (SCTDR) is not
transmitted.
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in asynchronous mode. In synchronous mode, a parity bit is neither added
nor checked, regardless of the PE setting.
Bit 5: PE
Description
0
Parity bit not added or checked
1
Parity bit added and checked^*
(Initial value)
Note: * When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the
parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
Bit 4—Parity Mode (O/E): Selects even or odd parity when parity bits are added and checked.
The O/E setting is used only in asynchronous mode and only when the parity enable bit (PE) is set
to 1 to enable parity addition and checking. The O/E setting is ignored in synchronous mode, or in
asynchronous mode when parity addition and checking is disabled.
Bit 4: O/E
Description
0
Even parity^*1
(Initial value)
1
Odd parity^*2
Notes: 1. If even parity is selected, the parity bit is added to transmit data to make an even
number of 1s in the transmitted character and parity bit combined. Receive data is
checked to see if it has an even number of 1s in the received character and parity bit
combined.
2. If odd parity is selected, the parity bit is added to transmit data to make an odd number
of 1s in the transmitted character and parity bit combined. Receive data is checked to
see if it has an odd number of 1s in the received character and parity bit combined.
Rev. 5.00, 09/03, page 435 of 760