SH7709S Datasheet, PDF (652/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

19.12.2 Port L Data Register (PLDR)
Bit:
Initial value:
R/W:
7
PL7DT
0
R
6
PL6DT
0
R
5
PL5DT
0
R
4
PL4DT
0
R
3
PL3DT
0
R
2
PL2DT
0
R
1
PL1DT
0
R
0
PL0DT
0
R
The port L data register (PLDR) is an 8-bit read-only register that stores data for pins PTL7 to
PTL0. Bits PL7DT to PL0DT correspond to pins PTL7 to PTL0. When the function is general
input port, if the port is read, the corresponding pin level is read. Table 19.22 shows the function
of PLDR.
PKDR is initialized to H'00 by power-on reset. It retains its previous value in software standby
mode and sleep mode, and in a manual reset.
The port L is also used as an analog pin, therefore does not have a pull-up MOS.
Table 19.22 Port L Data Register (PLDR) Read/Write Operation
PLnMD1
0
1
PLnMD0
0
1
0
1
Pin State
Other function
(see table 18.1)
Reserved
Input
Input
Read
H'00
H'00
Pin state
Pin state
Write
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
Ignored (no effect on pin state)
(n = 0 to 7)
Rev. 5.00, 09/03, page 608 of 760