SH7709S Datasheet, PDF (152/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Table 5.5 Way Replacement when Instructions Except for PREF Instruction Ended Up in
a Cache Miss
DSP bit W3LOAD W3LOCK W2LOAD
0
*
*
*
1
*
0
*
1
*
0
*
1
*
1
*
1
*
1
*
*: Don't care
Do not set as W3LOAD=1 and also W2LOAD=1
W2LOCK
*
0
1
0
1
Way to be replaced
Depends on LRU (table 5.2)
Depends on LRU (table 5.2)
Depends on LRU (table 5.6)
Depends on LRU (table 5.7)
Depends on LRU (table 5.8)
Table 5.6 LRU and Way Replacement (when W2LOCK=1)
LRU (5–0)
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
3
1
0
Table 5.7 LRU and Way Replacement (when W3LOCK=1)
LRU (5–0)
000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011
000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111
110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
Way to be Replaced
2
1
0
Table 5.8 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)
LRU (5–0)
000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,
010100, 010110, 011110, 011111
100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,
111011, 111100, 111110, 111111
Way to be Replaced
1
0
Rev. 5.00, 09/03, page 108 of 760