SH7709S Datasheet, PDF (301/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit: 15
14
13
12
11
10
9
8
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
10.2.12 Cautions on Accessing Refresh Control Related Registers
RFCR, RTCSR, RTCNT, and RTCOR require that a specific code be appended to the data when it
is written to prevent data from being mistakenly overwritten by program overruns or other write
operations (figure 10.5). Perform reads and writes using the following methods:
1. When writing to RFCR, RTCSR, RTCNT, and RTCOR, use only word transfer instructions.
Byte transfer instructions cannot be used.
When writing to RTCNT, RTCSR, or RTCOR, place B'10100101 in the upper byte and the
write data in the lower byte. When writing to RFCR, place B'101001 in the upper 6 bits and
the write data in the remaining bits, as shown in figure 10.5.
2. When reading from RFCR, RTCSR, RTCNT, and RTCOR, carry out reads with a 16-bit
width. 0 is read from undefined bits.
15
87
0
RTCSR, RTCNT, _{1 0 1 0 0 1 0 1}
RTCOR
15
10 9
Write data
0
RFCR 1 0 1 0 0 1
Write data
Figure 10.5 Writing to RFCR, RTCSR, RTCNT, and RTCOR
Rev. 5.00, 09/03, page 257 of 760