SH7709S Datasheet, PDF (183/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 4—IRQ4 Interrupt Request (IRQ4R): Indicates whether there is interrupt request input to
the IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by
clearing the IRQ4R bit.
Bit 4: IRQ4R
0
1
Description
No interrupt request input to IRQ4 pin
Interrupt request input to IRQ4 pin
(Initial value)
Bit 3—IRQ3 Interrupt Request (IRQ3R): Indicates whether there is interrupt request input to
the IRQ3 pin. When edge detection mode is set for IRQ3, an interrupt request is cleared by
clearing the IRQ3R bit.
Bit 3: IRQ3R
0
1
Description
No interrupt request input to IRQ3 pin
Interrupt request input to IRQ3 pin
(Initial value)
Bit 2—IRQ2 Interrupt Request (IRQ2R): Indicates whether there is interrupt request input to
the IRQ2 pin. When edge detection mode is set for IRQ2, an interrupt request is cleared by
clearing the IRQ2R bit.
Bit 2: IRQ2R
0
1
Description
No interrupt request input to IRQ2 pin
Interrupt request input to IRQ2 pin
(Initial value)
Bit 1—IRQ1 Interrupt Request (IRQ1R): Indicates whether there is interrupt request input to
the IRQ1 pin. When edge detection mode is set for IRQ1, an interrupt request is cleared by
clearing the IRQ1R bit.
Bit 1: IRQ1R
0
1
Description
No interrupt request input to IRQ1 pin
Interrupt request input to IRQ1 pin
(Initial value)
Bit 0—IRQ0 Interrupt Request (IRQ0R): Indicates whether there is interrupt request input to
the IRQ0 pin. When edge detection mode is set for IRQ0, an interrupt request is cleared by
clearing the IRQ0R bit.
Bit 0: IRQ0R
0
1
Description
No interrupt request input to IRQ0 pin
Interrupt request input to IRQ0 pin
(Initial value)
Rev. 5.00, 09/03, page 139 of 760