SH7709S Datasheet, PDF (565/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 6—Receive Interrupt Enable (RIE): Enables or disables the receive-data-full (RXI) and
receive-error (ERI) interrupts requested when serial receive data is transferred from the receive
shift register (SCRSR) to the receive FIFO data register (SCFRDR), when the quantity of data in
the receive FIFO register becomes more than the specified receive trigger number, and when the
RDRF flag in SCSSR is set to1.
Bit 6: RIE
Description
0
Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and receive break
interrupt (BRI) requests are disabled^*
(Initial value)
1
Receive-data-full interrupt (RXI) and receive-error interrupt (ERI) requests are
enabled
Note: * RXI and ERI interrupt requests can be cleared by reading the DR, ER, or RDF flag after it
has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. With the RDF flag,
read 1 from the RDF flag and clear it to 0, after reading receive data from SCRDR until the
quantity of receive data becomes less than the specified receive trigger number.
Bit 5—Transmit Enable (TE): Enables or disables the SCIF serial transmitter.
Bit 5: TE
Description
0
Transmitter disabled
1
Transmitter enabled^*
(Initial value)
Note: * Serial transmission starts after writing of transmit data into SCFTDR2. Select the transmit
format in SCSMR2 and SCFCR2 and reset the TFIFO before setting TE to 1.
Bit 4—Receive Enable (RE): Enables or disables the SCIF serial receiver.
Bit 4: RE
Description
0
Receiver disabled^*1
1
Receiver enabled^*2
(Initial value)
Notes: 1. Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, FER, PER, and
ORER). These flags retain their previous values.
2. Serial reception starts when a start bit is detected. Select the receive format in
SCSMR2 before setting RE to 1.
Bits 3 and 2—Reserved: These bits are always read as 0. The write value should always be 0.
Rev. 5.00, 09/03, page 521 of 760