SH7709S Datasheet, PDF (422/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 0—Count Start 0 (STR0): Selects whether to operate or halt CMCNT0.
Bit 0: STR0
0
1
Description
CMCNT0 count operation halted
CMCNT0 count operation
(Initial value)
Compare Match Timer Control/Status Register 0 (CMCSR0)
The compare match timer control/status register 0 (CMCSR0) is a 16-bit register that indicates the
occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the
clock used for incrementation. It is initialized to H'0000 by a reset, but retains its previous value in
standby mode.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
CMF
—
—
—
—
Initial value: 0
0
0
0
0
R/W: R/(W)^* R/W
R
R
R
Note: * The only value that can be written is 0 to clear the flag.
2
1
0
—
CKS1 CKS0
0
0
0
R
R/W R/W
Bits 15 to 8 and 5 to 2—Reserved: These bits are always read as 0. The write value should
always be 0.
Bit 7—Compare Match Flag (CMF): Indicates whether or not the compare match timer counter
0 (CMCNT0) and compare match timer constant 0 (CMCOR0) values match.
Bit 7: CMF
0
1
Description
CMCNT0 and CMCOR0 values do not match
(Initial value)
Clearing condition: Write 0 to CMF after reading CMF = 1
CMCNT0 and CMCOR0 values match
Rev. 5.00, 09/03, page 378 of 760