SH7709S Datasheet, PDF (209/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Bit 6—PC Break Select B (PCBB): Selects the break timing of the instruction fetch cycle for
channel B as before or after instruction execution.
Bit 6: PCBB
0
1
Description
PC break of channel B is set before instruction execution
PC break of channel B is set after instruction execution
(Initial value)
Bits 5 and 4—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 3—Sequence Condition Select (SEQ): Selects two conditions of channels A and B as
independent or sequential.
Bit 3: SEQ
0
1
Description
Channels A and B are compared under the independent condition (Initial value)
Channels A and B are compared under the sequential condition (channel A, then
channel B)
Bits 2 and 1—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 0—The Number of Execution Times Break Enable (ETBE): Enable the execution-times
break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the
number of break conditions matches with the number of execution times that is specified by the
BETR register.
Bit 0: ETBE
0
1
Description
The execution-times break condition is masked on channel B
The execution-times break condition is enabled on channel B
(Initial value)
Rev. 5.00, 09/03, page 165 of 760