SH7709S Datasheet, PDF (122/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Start
SH = 0
No _{and (MMUCR.SV = 0}
or SR.MD = 0)?
No
VPNs match?
No
Yes
Yes
VPNs
and ASIDs
match?
Yes
TLB miss
exception
User mode
V = 1?
Yes
User or
privileged?
No
TLB invalid
exception
Privileged mode
PR check
00/01 10
W
R/W?
R
11
W
R/W?
R
No
D = 1?
PR check
01/11 00/10
W
R/W?
W
R/W?
R
R
TLB protection
violation
exception
Yes
TLB protection
violation
Initial page
write
exception
No (noncacheable)
Memory
access
C = 1?
Yes (cacheable)
Cache
access
Figure 3.11 MMU Exception Generation Flowchart
Rev. 5.00, 09/03, page 78 of 760