SH7709S Datasheet, PDF (390/807 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series

Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR)
DE, DME = 1 and
No
AE, NMIF, TE = 0?
Yes
Transfer request?*¹
No
Yes
Transfer (1 transfer unit);
DMATCR − 1 → DMATCR,
SAR and DAR updated
*²
Bus mode,
*³
transfer request mode,
DREQ detection selection
system
No
DMATCR = 0?
Yes
DEI interrupt request (when IE = 1)
Does
AE = 1 or
No
NMIF = 1 or
DE = 0 or DME
= 0?
Yes
Transfer end
AE = 1 or
NMIF = 1 or
No
DE = 0 or
DME = 0?
Yes
Transfer aborted
Normal end
Notes: 1. In auto-request mode, transfer begins when AE, NMIF, and TE are both 0 and the DE and
DME bits are set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
Figure 11.2 DMAC Transfer Flowchart
Rev. 5.00, 09/03, page 346 of 760